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QPHY-DDR2

QPHY-DDR2

The Teledyne LeCroy QPHY-DDR2 Test Solution is the best way to characterize DDR2 memory interfaces. Capable of performing measurements on 400 MHz, 533 MHz, 667 MHz, 800 MHz, 1066 MHz and custom speed grades, QPHY-DDR2 has a full suite of Clock, Electrical and Timing tests as specified by the JEDEC Specification and Intel JEDEC Specifications Addendums.
QPHY-BroadR-Reach Automotive Ethernet enables faster data communication to meet the demands of today’s vehicles and the connected vehicles of the future. QPHY-BroadR-Reach automates testing and validation of 100 Mb/s Automotive Ethernet, which is described in both the BroadR-Reach and 100Base-T1 (IEEE 802.3bw) specifications.
DDR Debug Toolkit The DDR Debug Toolkit provides test, debug and analysis tools for the entire DDR design cycle. The unique DDR analysis capabilities provide automatic Read and Write burst separation, bursted data jitter analysis and DDR-specific measurement parameters.
ET-PMT Electrical Telecom Mask Test Package
GRL-USB-PD GRL-USB-PD software provides a simple and efficient way to perform USB-PD electrical parametric and protocol measurements. GRL-USB-PD provides waveform visibility and protocol analysis making it ideal for design and debug of USB Type-C Power Delivery silicon and end products.
GRL-USB-PD-C1 GRL-USB-PD-C1 is a flexible test controller, designed for USB-PD Compliance testing of the Unit Under Test (UUT) and more.
LNES Low Noise Edge Shaper
QPHY-10GBase-KR The Teledyne LeCroy QPHY-10GBase-KR solution automates testing for 10Gigabite Ethernet Copper Backplane base on the IEEE 802.3ap specifications. The test framework simplifies the test setup and execution of generic and common test requirements such as jitter separation, rise/fall time and transmitter equalization parameters. The guided wizard prompts the user to for specification required patterns and takes the measurements accordingly. The test report includes the test results pass/fail summary, margins and limits, as well as waveforms and measurements used during the test process.
QPHY-10GBASE-T QPHY-10GBASE-T automated compliance test software performs electrical compliance testing of the Physical Media Attachment (PMA) for 10GBASE-T Ethernet PHY, based on IEEE802.3-2008 requirements.
QPHY-DDR2 The Teledyne LeCroy QPHY-DDR2 Test Solution is the best way to characterize DDR2 memory interfaces. Capable of performing measurements on 400 MHz, 533 MHz, 667 MHz, 800 MHz, 1066 MHz and custom speed grades, QPHY-DDR2 has a full suite of Clock, Electrical and Timing tests as specified by the JEDEC Specification and Intel JEDEC Specifications Addendums.
QPHY-DDR3 The Teledyne LeCroy QPHY-DDR3 Test Solution is the best way to characterize DDR3, DDR3L, and LPDDR3 memory interfaces. Capable of performing measurements on 800 MT/s, 1066 MT/s, 1333 MT/s, 1600 MT/s, 1866 MT/s, 2133 MT/s and custom speed grades, QPHY-DDR3 has a full suite of Clock, Electrical, and Timing tests as specified by the JEDEC Specification.
QPHY-DDR4 DDR4 is an evolutionary upgrade from DDR3. It introduces data transfer rates which are nearly double the DDR3 transfer rates, ranging from 1.6 GT/s up to 3.2 GT/s. DDR4's higher transfer rates and lower operating voltage have driven new test methodologies and test requirements which were not previously required for DDR3 in order to ensure proper signal fidelity. QPHY-DDR4 has a full suite of Clock, Electrical, and Timing tests as specified by the JEDEC Specification which will aid in DDR4 design validation.
QPHY-DisplayPort The QPHY-DisplayPort software option provides an automated test environment for running all of the normative real-time oscilloscope tests for sources in accordance with Version 1.2b of the Video Electronics Standards Association (VESA) DisplayPort PHY Compliance Test Specification, as well as tests for HBR3 signals at 8.1 Gbps.
QPHY-eDP QPHY-eDP provides a highly automated and easy-to-use solution for Embedded DisplayPort source testing in accordance with version 1.4 of the VESA Embedded DisplayPort PHY compliance test guideline.
QPHY-ENET Ethernet testing compliant with IEEE 802.3-2005 requires many test setups and connections and mask tests. Using Teledyne LeCroy QualiPHY-ENET these measurements are easy to setup and complete. Instructive connection diagrams and message boxes appear as pop ups on the oscilloscope screen. The connection diagram instructs the user how to change test fixture and jumper pins in order to do complete test. When the tests are complete, QualiPHY will generate a test report in PDF, HTML, or XML formats. Jitter and pulse mask tests are performed with automatic waveform alignment, and all test results feature pass/fail indicators corresponding to the standard being tested.
QPHY-HDMI2 automated and easy-to-use solution for HDMI transmitter testing in accordance with Version 2.0 of the HDMI Compliance Test Specification (including testing for version 1.4 devices).
QPHY-LPDDR2 The Teledyne LeCroy QPHY-LPDDR2 Test Solution is the best way to characterize LPDDR2 memory interfaces. Capable of performing measurements on 466 MHz, 533 MHz, 667 MHz, 800 MHz, 900 Mhz, 1066 MHz and custom speed grades, QPHY-LPDDR2 has a full suite of Clock, Electrical and Timing tests as specified by the JEDEC Specifications.
QPHY-MIPI-DPHY - D-PHY Compliance Package Test Solution provides automated control for Teledyne LeCroy oscilloscopes for performing transmitter physical layer tests as described by the MIPI Alliance Specification for D-PHY version 1.00.00
QPHY-MIPI-MPHY The QPHY-MIPI-MPHY Test Solution provides automated control of Teledyne LeCroy oscilloscopes for performing transmitter physical layer tests as described by the MIPI Alliance Specification for M-PHY version 3.0.
QPHY-MOST150 The Teledyne LeCroy QPHY-MOST150 compliance test package provides a highly automated and easy-to-use solution to MOST compliance testing. QPHY-MOST150 will perform all electrical compliance tests as defined in the MOST150 oPHY Automotive Physical Layer Sub-Specification Rev. 1.1 and MOST150 cPHY Automotive Physical Layer Sub-Specification Rev 1.0.
QPHY-MOST50 The Teledyne LeCroy QPHY-MOST50 compliance test package provides a highly automated and easy-to-use solution to MOST compliance testing. QPHY-MOST50 will perform all electrical compliance tests as defined in the MOST Electrical Physical Layer Specification Rev. 1.1.
QPHY-PCIe The Teledyne LeCroy QPHY-PCIe Test Solution provides automated control for Teledyne LeCroy oscilloscopes for performing the entire transmitter physical layer tests as described by the Card Electro-mechanical specification Rev 1.1 and 2.0
QPHY-PCIe3 Teledyne LeCroy QPHY-PCIe3 Test Solution provides automated control for Teledyne LeCroy oscilloscopes for performing transmitter physical layer tests as described by the PCI Express Base Specification Revision 3.0 Version 0.9 and the Card Electromechanical Specification Revision 3.0 Version 0.7.
QPHY-SAS2 The Teledyne LeCroy QPHY-SAS2 Test Solution provides automated control for the SDA 8 Zi series of oscilloscopes for performing all of the transmitter physical layer tests as described by version 1.01 of the UNH IOL Serial Attached SCSI (SAS) Consortium SAS-2 6Gb/s Physical Layer Test Suite. This specification covers targets and initiators running at 1.5 Gb/s, 3.0 Gb/s and 6.0 Gb/s.
QPHY-SAS3 The QPHY-SAS3 Test Solution provides automated control of the SDA 8 Zi-A and LabMaster 10 Zi oscilloscopes for performing all of the transmitter physical layer tests as described by the T10 SAS-3 specification. This specification covers targets and initiators running at 1.5 Gb/s, 3.0 Gb/s, 6.0 Gb/s, and 12.0 Gb/s.
QPHY-SATA-TSG-RSG for SATA compliance testing to be used in conjunction with the PeRT3. By leveraging the capabilities of both the oscilloscope and the PeRT3, QPHY-SATA-TSG-RSG can automatically perform all of the PHY, TSG, OOB, and RSG tests as described by the SATA UTD 1.5. Furthermore, QPHY-SATA-TSG can be configured to test Gen1, Gen2, and Gen3 SATA PUTs.
QPHY-SFI The Teledyne LeCroy QPHY-SFI solution automates testing for SFI base on the SFF 8431 specifications. The test framework simplifies the test setup and execution of generic and common test requirements such as jitter separation, rise/fall time and transmitter equalization parameters. The guided wizard prompts the user to for specification required patterns and takes the measurements accordingly. The test report includes the test results pass/fail summary, margins and limits, as well as waveforms and measurements used during the test process.
QPHY-USB The USB package provides a complete acquisition and analysis system for USB 2.0 devices, hosts, and hubs, as specified in the USB-IF USB 2.0 Electrical Test Specification. The test software implements a full set of electrical tests for USB 2.0, including High-, Full-, and Low-speed tests and is supported by Teledyne LeCroy’s QualiPHY automated test and reporting software.
QPHY-USB3-Tx-Rx SuperSpeed USB is one of most highly anticipated standards in several years. At 10x the data rate of USB 2.0 and with new features like CTLE (continuous time linear equalization) and reference channels, SuperSpeed USB will pose new challenges to implementers.
QPHY-USB3.1-Tx-Rx QPHY-USB3.1-Tx-Rx offers an automated test package for USB 3.1 transmitter and receiver compliance testing, characterization, and debug.
Key Features

  • Support for testing 400 MHz, 533 MHz, 667 MHz, 800 MHz, 1066 MHz and custom speed grades of DDR2 signals
  • Fastest way to gain confidence in your DDR2 interface by measuring a large number of cycles and reporting statistical results
  • Fully annotated worst case measure ment screenshot captured and displayed in report including trace labels and pertinent voltage levels
  • Stop on test/failure capability allows the user to pause at a particular test and review the measure on the oscilloscope display
  • Complete test coverage for tests as described by the JESD79-2E and JESD208 JEDEC Specifications and Intel DDR2 667/800 JEDEC Specifications Addendum Rev. 1.1 and Intel DDR2 400/ 533 JEDEC Specifications Addendum Rev. 1.0

The Teledyne LeCroy QPHY-DDR2 Test Solution is the best way to characterize DDR2 memory interfaces. Capable of performing measurements on 400 MHz, 533 MHz, 667 MHz, 800 MHz, 1066 MHz and custom speed grades, QPHY-DDR2 has a full suite of Clock, Electrical and Timing tests as specified by the JEDEC Specification and Intel JEDEC Specifications Addendums.

The Teledyne LeCroy QualiPHY platform provides an easy to configure user interface, allows for custom test and limit selection, displays connection diagrams to the user to ensure proper connectivity, and generates reports with all of the results including screenshots of the worst case failures for each applicable test. In addition, all of the waveforms tested by QPHY-DDR2 can be saved to easily share information or rerun the tests at a later time.

QPHY-DDR2 enables the user to obtain the highest level of confidence in their DDR2 interface. Due to the high level of variability in DDR2 measurements it is important to measure a large number of cycles. By measuring a large number of cycles in a very short period of time the user can be more confident that they are catching the true maximum and minimum points for their measurement.

In addition to automated characterization of DDR2 signals, QPHY-DDR2 also enables powerful debug capability for DDR2 signals inside the oscilloscope. Root causes of failure can be quickly and easily found using all of the advanced serial data tools within the oscilloscope. These include: SDA II, Eye Doctor™ II, WaveScan™, and many more.

Clock Tests – These tests perform all of the clock test as described by the appropriate JEDEC specification. These include average clock period, absolute clock period, average high/low pulse width, absolute high/low pulse width, half period jitter, clock period jitter, cycle-to-cycle period jitter and cumulative error over n period tests.

Electrical Tests – These tests measure the electrical characteristics of the DDR2 signals. Shown above, the SoutR test measures the slew rates of the data, strobe and clock signals. Over 1000 slew rate measurements were performed and the worst instance was displayed on the screen. The signals are annotated with the signal names to make the screen easy to interpret. Additionally, cursors are used to show the user the voltage levels between which the slew rate was measured.

Timing Test – These tests verify the timing relationship between particular DDR2 events. Shown above, the tDQSCK test verifies that the strobe output access time from the clock signal is within the limit specified by the appropriate JEDEC specification. In this test, 5000 tDQSCK measurements were performed on all of the DDR2 read bursts and the worst instance was displayed on the screen.

Eye Diagrams – Eye Diagrams are a powerful tool for debugging serial data signals. QPHY-DDR2 enables the user to create eye diagrams of both the Read and the Write data bursts to ensure that the signal integrity is sufficient such that the data will be sampled properly by the receiver.

QualiPHY has many preset compliance configurations but also enables users to create their own configuration and limit sets.

Connection Diagrams prompt the user to make the necessary connections..

Compliance Reports contain all of the tested values, the specific test limits and screen captures. Compliance Reports can be created as HTML, PDF or XML.

QualiPHY

QualiPHY is designed to reduce the time, effort and specialized knowledge needed to perform compliance testing on high-speed serial buses.

  • Guides the user through each test setup
  • Performs each measurement in accordance with the relevant test procedure
  • Compares each measured value with the applicable specification limits
  • Fully documents all results
  • QualiPHY helps the user perform testing the right way -- every time!

Specifications

Clock Tests
tCK(avg) – Average Clock Period
tCH(avg) – Average High Pulse Width
tCL(avg) – Average Low Pulse Width
tCK (abs) – Absolute Clock Period
tCH(abs) – Absolute High Pulse Width
tCL(abs) – Absolute Low Pulse Width
tJIT(duty) – Half Period Jitter
tJIT(per) – Clock Period Jitter
tJIT(cc) – Cycle to Cycle Period Jitter
tERR(n per) – Cumulative error

Advanced Debug
Eye Diagram of Data and Strobe on Read Cycle
Eye Diagram of Data and Strobe on Write Cycle

Electrical Tests
SlewR – Input Rising Edge Slew Rate
SlewF – Input Falling Edge Slew Rate
VIH(ac) – AC Input Logic High
VIH(dc) – DC Input Logic High
VIL(ac) – AC Input Logic Low
VIL(dc) – DC Input Logic Low
VSWING – Input Signal Maximum
Peak to Peak Swing
SoutR – Output Slew Rate Rise
SoutF – Output Slew Rate Fall
tSLMR – Output Slew Rate Matching Ratio
AC Overshoot Peak Amplitude
AC Overshoot Area Above VDDQ
AC Undershoot Peak Amplitude
AC Undershoot Area Below VSSQ
VID(ac) – AC Differential Input Voltage
VIX(ac) – AC Differential Input Cross Point Voltage
VOX(ac) – AC Differential Output Cross Point Voltage

Timing Tests
tHZ(DQ) – DQ High Impedance Time from CK/CK#
tLZ(DQ) – DQ Low Impedance Time from CK/CK#
tLZ(DQS) – DQS Low Impedance Time from CK/CK#
tHP – CK Half Pulse Width
tQHS – DQ Hold Skew Factor
tQH – DQ/DQS Output Hold Time from DQS
tDQSH – DQS Input High Pulse Width
tDQSL – DQS Input Low Pulse Width
tDSS – DQS Falling Edge to CK Setup Time
tDSH – DQS Falling Edge Hold Time from CK
tWPRE – Write Preamble
tWPST – Write Postamble
tRPRE – Read Preamble
tRPST – Read Postamble
tDQSQ – Skew between DQS and DQ
tDQSS – DQS Latching Transition to Clock Edge
tDQSCK – DQS Output Access Time from CK/CK#
tAC – DQ Output Access Time from CK/CK#
tDS(base) – DQ and DM Input Setup Time
tDH(base) – DQ and DM Input Hold Time
tIS(base) – Address and Control Input Setup Time
tIH(base) – Address and Control Input Hold Time
tDS1(base) – DQ and DM Input Setup Time (Single-ended Strobe)
tDH1(base) – DQ and DM Input Hold Time (Single-ended Strobe)